Memory chip and apparatus for testing a memory chip

ABSTRACT

The present invention provides a memory chip ( 100 ) which can be operated in a normal mode and in a test mode (TM) and which has a device ( 102 ) for outputting data from the memory chip ( 100 ) and a device ( 104 ) for enabling the device ( 102 ) for outputting data when the test mode (TM) has been activated. The device ( 104 ) for enabling the device ( 102 ) for outputting data has a device for masking data so that only particular portions of the data are output when a data masking state (DQM) has been activated.

[0001] The present invention relates to a memory chip and to anapparatus for testing a memory chip.

[0002] To be able to guarantee the operability of memory chips over arelatively long period, the memory chips are subjected to artificialaging. If the error rate of memory chips is plotted over their age, thenthe result is a characteristic curve similar to the shape of a bath tub,i.e. most of the chips are faulty from the outset or become faulty onlyafter an extended time. Artificial aging, generally called burn-in, iscarried out in a type of furnace at raised temperature and at raisedinternal electrical operating voltages.

[0003] During artificial aging of the memory chips, said memory chipsare operated in a test mode in which, normally, the internal voltagesources for the memory chips are first disconnected and replaced byexternal voltage sources having higher supplied voltages, and secondlythe data which the memory chips output have been inverted. During thetest mode, data are written to the memory chips continuously and areread therefrom continuously.

[0004] A crucial quality criterion for artificial aging is that thememory chips remain in the test mode throughout the artificial agingprocess, since otherwise there is no assurance of their being loaded bythe raised internal voltages. To be able to single out memory chipswhich are not in the test mode, activation of the test mode needs to beconstantly checked.

[0005] Activation of the test mode is normally checked by checkingwhether a memory chip delivers inverted data, in line with the test modestipulations. If this his not the case, the memory chip is faulty and/oris assessed as faulty by a tester and can be singled out.

[0006] A drawback of checking activation of the test mode using theinverted data is that additional inverters need to be held in the memorychips in order to invert the data, which increases the memory chips'circuit complexity, required chip area, etc.

[0007] Another drawback is that, in the memory chip's normal operatingmode or normal mode, the required inverters encumber and slow down thedata path in the memory chip, since they are always contained in thedata path. This is due to the extended delay times through the inverterinfrastructure, such as through lines, latches, etc., and to loads, suchas capacitive loads, arising as a result of the inverters in the datapath.

[0008] The object of the present invention is to provide a memory chipand an apparatus and a method for testing a memory chip which permitmemory chips to be tested with little complexity without adverselyaffecting the performance of the memory chips.

[0009] This object is achieved by a memory chip in accordance with claim1, by an apparatus for testing a memory chip in accordance with claim 8and by a method for testing a memory chip in accordance with claim 10.

[0010] The subclaims contain advantageous developments and improvementsof the memory chip specified in claim 1 and of the apparatus for testinga memory chip specified in claim 8.

[0011] In accordance with one preferred development of the memory chipof the present invention, the device for enabling the device foroutputting data has a device for masking data so that only particularportions of the data are output when a data masking state has beenactivated.

[0012] In accordance with another preferred development of the memorychip, the enabling device enables the device for outputting data whenthe data masking state and the test mode have been activated, and doesnot enable the device for outputting data when the data masking statehas been activated and the test mode has not been activated.

[0013] In accordance with another preferred development of the memorychip, the enabling device has a NOR gate (NOR) which combines the logicstate of the test mode with the negated logic data masking state.

[0014] In accordance with another preferred development of the memorychip, the device for outputting data has an off-chip driver (OCD).

[0015] In accordance with another preferred development of the memorychip, said memory chip additionally has internal voltage sources whichcan be deactivated when the test mode has been activated.

[0016] In accordance with another preferred development of the memorychip, the memory chip has a synchronous dynamic random access memory(SDRAM).

[0017] In accordance with one preferred development of the apparatus fortesting a memory chip, the apparatus for testing a memory chip has adevice for activating and deactivating the data masking state of thememory chip, which device activates the data masking state when thememory chip is operated in the test mode.

[0018] Preferred exemplary embodiments of the present invention areexplained in more detail below with reference to the appended drawings,in which:

[0019]FIG. 1 shows an exemplary embodiment of a memory chip inaccordance with the present invention; and

[0020]FIG. 2 shows an exemplary embodiment of a testing apparatus inaccordance with the present invention.

[0021]FIG. 1 shows an exemplary embodiment of a memory chip inaccordance with the present invention. The memory chip 100 can beoperated in a normal mode or normal operating mode and in a test modeand is typically split into a cell array and a peripheral array. Thememory chip 100 preferably comprises a synchronous dynamic random accessmemory (SDRAM) and additionally preferably comprises internal voltagesources which can be deactivated when the test mode has been activated.This opportunity for deactivation of the memory chip's internal voltagesources is used, as already mentioned above, to replace application ofthe relatively low internal operating voltages of the memory chip 100with application of external voltages having a much higher voltage valueduring artificial aging of the memory chip.

[0022] With further reference to FIG. 1, the memory chip 100additionally has a device 102 for outputting data from the memory chip100 and a device 104 for enabling the device 102 for outputting datawhen the test mode has been activated.

[0023] The device 102 for outputting data from the memory chip 100preferably has an off-chip driver (OCD) which is located in theperipheral zone of the memory chip 100 and, by way of example, amplifiesinternal signals of the memory chip 100 or adjusts the level of internalsignals from an internal level to an external level for signals outsidethe memory chip 100, in order to be able to operate the memory chip 100in external circuits.

[0024] The device 104 for enabling the device 102 for outputting datapreferably has a device for masking the data so that, when a datamasking state or data-mask state (DQM) has been activated, onlyparticular portions of the data delivered by the device 102 foroutputting data are output. The data are preferably represented bydigital signals, and the data are masked, by way of example, in order toselect particular bits in a packet or burst of bits, which simplifiestesting of the memory chip. Externally, a memory chip preferably alsohas a DQM contact pin which, when a signal is applied thereto, causesindividual bits in a block of bits to be filtered out.

[0025] The enabling device 104 preferably enables the device 102 foroutputting data when both the data masking state (DQM) and the test mode(TM) have been activated, and does not enable the device 102 foroutputting data when only the data masking state (DQM) has beenactivated and the test mode (TM) has not been activated. In theexemplary embodiment shown in FIG. 1, the enabling device 104 preferablyhas a NOR gate (NOR) which combines the logic state of the test mode(TM) at an input 106 of the NOR gate with the negated logic data maskingstate (DQM) at another input 108 of the NOR gate in order to producetherefrom an output signal 110 or enable signal at an output of the NORgate. The enabling device 104 can have any other suitable combination oflogic gates in order to implement its function.

[0026] In the exemplary embodiment of a memory chip 100 in accordancewith the present invention, as shown in FIG. 1, the device 102 foroutputting data is activated, as mentioned, by the enabling device 104,in this case the NOR gate, when the test mode (TM) has been activated.In addition, the data masking state (DQM) likewise needs to have beenactivated, however, in order for the output signal 110 from the enablingdevice 104 to enable or activate the device 102 for outputting data.Depending on the state of the device 102 for outputting data, the outputof the memory chip 100 therefore either outputs a normal data signal, ifthe device 102 for outputting data has been activated, or has ahigh-impedance state, if the device 102 for outputting data has not beenactivated. The high-impedance state is a tri-state, for example, whichis produced by a push-pull output stage with tri-state circuitry for aninternal data bus in the memory chip 100 which the device 102 foroutputting data uses to deliver desired data. If the device 102 foroutputting data has not been enabled even though the data masking state(DQM) has been activated, then the high-impedance state at the output ofthe device 102 for outputting data can therefore be used to determinewhether or not the test mode (TM) has been activated correctly.Activation of the test mode is therefore determined using correct orabsent output of data rather than inverted data. If the data are output,the test mode (TM) has been activated or is active.

[0027] An output of the memory chip 100 preferably has a resistor 112connected to it, said resistor being connected to a terminating voltage(Vterm). In addition, a first input of a comparator 114 is connected tothe output of the memory chip 100. The other input of the comparator 114has a reference-ground voltage Vref applied to it which is compared withthe voltage drop across the resistor 112, said voltage appearing at theoutput of the device 102 for outputting data. If the output of thedevice 102 for outputting data is in a high-impedance state, e.g. atri-state, then the comparator measures the voltage Vterm, which, whenthe data masking state (DQM) has been activated, indicates duringtesting in the test mode that the test mode (TM) has not been activated.

[0028]FIG. 2 shows an apparatus 200 for testing a memory chip 202, whichis preferably a memory chip 100 as shown in FIG. 1 and is operated in atest mode. The apparatus 200 for testing the memory chip 202 has adevice 204 for continuously sending data to the memory chip 202 and forcontinuously receiving data from the memory chip 202, and a device 206for checking the activation of the test mode for the memory chip 202.The checking device 206 establishes or determines that the test mode hasbeen activated if the device 204 for continuously sending and receivingis continuously receiving data from the memory chip 202.

[0029] The apparatus 200 for testing a memory chip 202 preferablyadditionally has a device 208 for activating and deactivating the datamasking state (DQM) of the memory chip 202, and activates the datamasking state when the memory chip 202 is operated in the test mode(TM). The test mode (TM) for the memory chip 202 is likewise preferablyactivated by the testing apparatus 200.

[0030] The apparatus 200 for testing a memory chip 202, as shown in FIG.2, is suitable, as mentioned, for testing a memory chip 100 as shown inFIG. 1. In this case, the test mode is checked by virtue of dataconstantly being sent to the memory chip 202 and by virtue of dataconstantly being received from the memory chip 202. If the memory chip202 is operated in the test mode, which can likewise be set by thetesting apparatus 200, as mentioned above, the testing apparatus 200constantly receives data from the memory chip 202, which indicates thatthe test mode is in an activated state. If, on the other hand, the testmode has not been activated, then the memory chip 202 does not send anydata to the testing apparatus 200, and the voltage Vterm shown in FIG.1, for example, is applied to the input of the testing apparatus 200,since the device 102 (FIG. 1) for outputting data has a high-impedancestate at its output.

[0031] The device 104 for masking data is activated by the testingapparatus 200 using the device 208 for activating and deactivating thedata masking state, and is kept active throughout the entire test mode.As has been explained with reference to FIG. 1, the test mode thereforedetermines alone whether or not data are output, which means that it ispossible to check whether it has been activated.

[0032] Although the present invention has been described with referenceto preferred exemplary embodiments, it is not limited thereto, but canbe modified in a wide variety of ways.

[0033] One advantage of the present invention is that the describedmemory chip and the described testing apparatus make it possible todispense with the prior art's customary data inversion indicating thetest mode. This reduces the complexity of the memory chip and, inparticular, the chip area. This is due, inter alia, to it being possibleto dispense with inverters, latches, lines, etc.

[0034] Another advantage of the present invention is that omitting theinverters relieves the load on the data path within the memory chip, andfaster operation of memory chips is therefore made possible.

[0035] Another advantage of the present invention is that the circuitsrequired for enabling the device for outputting data or the off-chipdriver are already present in customary memory chips, such as an SDRAM.

[0036] List of reference numerals:

[0037] Memory chip

[0038] Device for outputting data

[0039] Device for enabling 102

[0040] Input of 104

[0041] Input of 104

[0042] Output signal from 104

[0043] Resistor

[0044] Comparator

[0045] Apparatus for testing a memory chip

[0046] Memory chip

[0047] Device for continuously sending data and receiving data

[0048] Device for checking activation of the test mode

[0049] Device for activating and deactivating the data masking state

1. Memory chip (100; 202) which can be operated in a normal mode and ina test mode (TM), having the following features: a device (102) foroutputting data from the memory chip (100; 202); and a device (104) forenabling the device (102) for outputting data when the test mode (TM)has been activated.
 2. Memory chip (100; 202) according to claim 1, inwhich the device (104) for enabling the device (102) for outputting datahas a device for masking data so that only particular portions of thedata are output when a data masking state (DQM) has been activated. 3.Memory chip (100; 202) according to claim 2, in which the enablingdevice (104) enables the device (102) for outputting data when the datamasking state (DQM) and the test mode (TM) have been activated, and doesnot enable it when the data masking state (DQM) has been activated andthe test mode (TM) has not been activated.
 4. Memory chip (100; 202)according to claim 6, in which the enabling device (104) has a NOR gate(NOR) which combines the logic state of the test mode (TM) with thenegated logic data masking state (DQM).
 5. Memory chip (100; 202)according to one of the preceding claims, in which the device (102) foroutputting data has an off-chip driver (OCD).
 6. Memory chip (100; 202)according to one of the preceding claims, which additionally hasinternal voltage sources which can be deactivated when the test mode(TM) has been activated.
 7. Memory chip (100; 202) according to one ofthe preceding claims, which has a synchronous dynamic random accessmemory (SDRAM).
 8. Apparatus (200) for testing a memory chip (100; 202)according to one of claims 1 to 7, the memory chip (100; 202) beingoperated in the test mode, having the following features: a device (204)for continuously sending data to the memory chip (100; 202) andreceiving data from the memory chip (100; 202); a device (206) forchecking the activation of the test mode (TM) for the memory chip (100;202); where the checking device (206) determines that the test mode (TM)has been activated if the device (204) for continuously sending andreceiving is continuously receiving data from the memory chip (100;202).
 9. Apparatus (200) for testing a memory chip (100; 202) accordingto claim 8, additionally having the following feature: a device (208)for activating and deactivating the data masking state (DQM) of thememory chip (100; 202), which device activates the data masking state(DQM) when the memory chip (100; 202) is operated in the test mode (TM).10. Method for testing a memory chip (100; 202) according to one ofclaims 1 to 7, the memory chip (100; 202) being operated in the testmode (TM), having the following steps: continuous sending of data to thememory chip (100; 202) and reception of data from the memory chip (100;202); checking of the activation of the test mode (TM) for the memorychip (100; 202); where the checking step determines that the test mode(TM) has been activated if data are continuously received from thememory chip (100; 202).
 11. Method for testing a memory chip (100; 202)according to claim 10, additionally having the following step:activation of the data masking state (DQM) of the memory chip (100; 202)when the memory chip (100; 202) is in the test mode (TM).